Features:
- The CPU 948 executes STEP 5 programs in S5-155U single- or multiprocessor racks.
- Integrated RAM, memory-card storage, and backup power serve separate program-retention roles.
- PG, optional serial, and S5 backplane interfaces connect engineering, communication, and I/O paths.
The operating system executes cyclic and interrupt-driven blocks from active memory.
The rack bus exchanges process-image data with modules and coordinates multiple CPUs.
Startup evidence links memory, backup, slot assignment, supply, and program state.
The Siemens 6ES5948-3UA13 S5-155U CPU 948 may remain available for quotation and support beyond End-Of-Life (EOL) by the manufacturer (OEM).
Siemens 6ES5948-3UA13 S5-155U CPU 948 Manuals,Datasheets,Link
Important Notice: Other accessories, manuals, cables, calibration data, software, etc. are not included with this equipment unless listed in the above stock item description. All prices are shown in USD.
Separating active execution from stored recovery data
- User RAM: The 640 KB memory holds active STEP 5 program and data content.
- Memory card: Non-volatile load information can be retained outside working RAM.
- Backup path: The backup circuit preserves assigned RAM content when rack power is removed.
- Archive: A verified STEP 5 project remains the external source for controlled recovery.
Scheduling the S5 program around operating-system events
- Cyclic blocks: The main control sequence repeats through the assigned organization structure.
- Timed events: Configured time bases call their associated program sections.
- Process interrupts: Field events invoke the corresponding interrupt organization blocks.
- Stop handling: Program and hardware conditions can move the CPU into the defined stop sequence.
Moving I/O and coordination data through the S5 bus
- Process image: Input and output values are exchanged with signal modules through the backplane.
- Direct areas: Additional addresses operate outside the ordinary cyclic image.
- Multiprocessor role: Several CPUs divide assigned tasks in the same central controller.
- Slot assignment: Every processor and submodule remains in the position defined by the system project.
Connecting program tools and optional communication hardware
- PG interface: A programming device reaches the CPU through the assigned PG path.
- Second interface: The optional submodule supplies the documented serial or communication service.
- Online comparison: Project blocks are checked against the active CPU contents.
- Recovery test: Program load, run transition, I/O exchange, and retained data are verified together.