Features:
- Forms the I/O boundary between field connections and regulator processors.
- Supports one-channel and multi-channel control layouts.
- Acquires each channel independently before controller use.
IS200ERIOH1A organizes external signal entry without executing the regulator algorithms performed by the controller processors.
A simplex layout follows one ERBP-based route, whereas redundant control separates M1, M2 and C through the required ERBP and ERRB hardware.
FPGA acquisition and dual-port memory isolate asynchronous field activity from processor access, keeping each regulator channel associated with its own data image.
For established EX2100 systems, Apter Power can assist with sourcing and original-document requests for the General Electric IS200ERIOH1A Exciter Regulator I/O Board.
General Electric IS200ERIOH1A Exciter Regulator I/O Board Manuals, Datasheets, Links
Important Notice: Other accessories, manuals, cables, calibration data, software, etc. are not included with this equipment unless listed in the above stock item description. All prices are shown in USD.
Single-channel arrangement
- Backplane: ERBP carries the simplex regulator I/O path.
- Transformer interface: EPCT supplies the applicable transformer-related connections.
- Terminal interface: ECTBG2 serves the simplex customer terminal path.
- Option hardware: ERDD and EROC add bridge and option-card functions.
Three-channel arrangement
- M1 path: The primary regulator retains its ERBP-based route.
- M2 path: ERRB hardware carries the second regulator channel.
- C path: A separate ERRB route supports the control channel.
- Redundant interfaces: ECTBG1 and ERRR provide topology-specific connections.
Acquisition sequence
- Serial entry: Incoming I/O reaches the board through channel connectors.
- FPGA control: Acquisition is managed independently for each regulator channel.
- Memory staging: Collected values are placed in dual-port memory.
- Processor access: DSPX reads the prepared channel-specific data image.
Backplane checks
- Topology: Identify simplex or redundant architecture before service.
- Backplane: Confirm whether the position belongs to ERBP or ERRB.
- Connector identity: Preserve both 25-pin serial I/O assignments.
- Channel population: Verify the installed M1, M2 and C controller arrangement.