Features:
- The CPU 948R processes STEP 5 programs inside an S5-155H central controller.
- Internal RAM and a removable flash EPROM memory card separate execution memory from retained load storage.
- Dedicated front LEDs distinguish run state, reset activity, interface faults and output disablement.
The module places its processor and RAM on two mechanically joined Eurocard boards that operate as one CPU assembly.
A front mode selector and reset switch control run, stop, overall reset and cold-restart sequences.
The serial programmer port stays available at the front while rack signals pass through the backplane connectors.
The Siemens 6ES5948-3UR23 SIMATIC S5 CPU 948R Central Processing Unit may still be available for purchase and support from Apter Power beyond End-Of-Life (EOL) by the manufacturer (OEM).
Siemens 6ES5948-3UR23 SIMATIC S5 CPU 948R Central Processing Unit Manuals,Datasheets,Link
Important Notice: Other accessories, manuals, cables, calibration data, software, etc. are not included with this equipment unless listed in the above stock item description. All prices are shown in USD.
How the CPU schedules STEP 5 work
- Cyclic Level: The normal scan repeatedly executes the assigned organization and program blocks.
- Timed Level: Time-grid and clock-controlled events start their configured processing independently of the base scan.
- Interrupt Level: Process interrupts arrive through the S5 bus and branch to their assigned block boundary handling.
- Soft Stop: The CPU can continue the designated stop-mode processing while normal digital outputs remain disabled.
Operating the CPU from the front plate
- Mode Selector: RUN and STOP positions define whether the user program scans or enters a soft stop.
- Reset Switch: Switch position selects overall reset, cold restart or cold restart with retained memory.
- Memory Receptacle: The front slot accepts the S5 flash EPROM used to restore the load image.
- Mechanical Lock: The lever and locking bolt secure the joined CPU boards in the prescribed central-rack slot.
Engineering and rack connections
- SI1 Port: A programmer can connect at the front regardless of the current CPU operating mode.
- SI2 Indication: The interface LED remains off in normal operation and reports an internal communication fault when lit.
- Rack Backplane: The central controller supplies the CPU and carries module access for the process image.
- SINEC H1 Option: A compatible communication processor can move engineering traffic over the parallel backplane path.
Interpreting the diagnostic indications
- QVZ: A timeout indicates that an addressed module, memory path or expansion connection no longer acknowledges.
- ADF: The program attempted to use an address absent from the configured process image.
- ZYK: Scan-time monitoring stopped cyclic processing after the watchdog limit was exceeded.
- BASP: Command output disablement forces digital outputs to the safe zero state.